25C080-ESLASHP datasheet(11/22 Pages) MICROCHIP

11 / 22 page

 2004 Microchip Technology Inc.

DS21230D-page 11

25AA080/25LC080/25C080

3.6

Write Status Register (WRSR)

The Write Status Register (WRSR) instruction allows the

user to select one of four levels of protection for the

array by writing to the appropriate bits in the Status reg-

ister. The array is divided up into four segments. The

user has the ability to write-protect none, one, two, or

all four of the segments of the array. The partitioning is

controlled as shown in Table 3-2.

The Write-Protect Enable (WPEN) bit is a nonvolatile

bit that is available as an enable bit for the WP pin. The

Write-Protect (WP) pin and the Write-Protect Enable

(WPEN) bit in the Status register control the program-

mable hardware write-protect feature. Hardware write

protection is enabled when WP pin is low and the

WPEN bit is high. Hardware write protection is disabled

when either the WP pin is high or the WPEN bit is low.

When the chip is hardware write-protected, only writes

to nonvolatile bits in the Status register are disabled.

See Table 3-3 for a matrix of functionality on the WPEN

bit.

See Figure 3-5 for the WRSR timing sequence.

TABLE 3-2:

ARRAY PROTECTION

FIGURE 3-7:

WRITE STATUS REGISTER TIMING SEQUENCE

BP1

BP0

Array Addresses

Write-Protected

none

upper 1/4

(0300h - 03FFh)

upper 1/2

(0200h - 03FFh)

all

(0000h - 03FFh)

1011

12131415

instruction

data to Status register

High-impedance

SCK

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