PIC12F683-ESLASHSN datasheet(91/148 Pages) MICROCHIP

91 / 148 page

 2004 Microchip Technology Inc.

Preliminary

DS41211B-page 89

PIC12F683

12.6

Watchdog Timer (WDT)

For PIC12F683, the WDT has been modified from

previous PIC12F683 devices. The new WDT is code and

functionally compatible with previous PIC12F683 WDT

modules and adds a 16-bit prescaler to the WDT. This

allows the user to have a scaler value for the WDT and

TMR0 at the same time. In addition, the WDT time-out

value can be extended to 268 seconds. WDT is cleared

under certain conditions described in Table 12-7.

12.6.1

WDT OSCILLATOR

The WDT derives its time base from the 31 kHz

LFINTOSC. The LTS bit does not reflect that the

LFINTOSC is enabled.

The value of WDTCON is ‘---0 1000’ on all Resets.

This gives a nominal time base of 16 ms, which is com-

patible with the time base generated with previous

PIC12F683 microcontroller versions.

A new prescaler has been added to the path between

the INTRC and the multiplexers used to select the path

for the WDT. This prescaler is 16 bits and can be

programmed to divide the INTRC by 128 to 65536, giv-

ing the time base used for the WDT a nominal range of

1 ms to 268s.

12.6.2

WDT CONTROL

The WDTE bit is located in the Configuration Word

When the WDTE bit in the Configuration Word register

is set, the SWDTEN bit (WDTCON<0>) has no effect.

If WDTE is clear, then the SWDTEN bit can be used to

enable and disable the WDT. Setting the bit will enable

it and clearing the bit will disable it.

The PSA and PS<2:0> bits (OPTION_REG) have the

same

function

in previous

versions

the

PIC12F683 family of microcontrollers. See Section 5.0

“Timer0 Module” for more information.

FIGURE 12-9:

WATCHDOG TIMER BLOCK DIAGRAM

TABLE 12-7:

WDT STATUS

Note:

When the Oscillator Start-up Timer (OST)

is invoked, the WDT is held in Reset,

because the WDT Ripple Counter is used

by the OST to perform the oscillator delay

count. When the OST count has expired,

the WDT will begin counting (if enabled).

Conditions

WDT

WDTE = 0

Cleared

CLRWDT

Command

Oscillator Fail Detected

Exit Sleep + System Clock = T1OSC, EXTRC, INTRC, EXTCLK

Exit Sleep + System Clock = XT, HS, LP

Cleared until the end of OST

31 kHz

PSA

16-bit WDT Prescaler

From TMR0 Clock Source

Prescaler(1)

PS<2:0>

PSA

WDT Time-out

To TMR0

WDTPS<3:0>

WDTE from Configuration Word register

SWDTEN from WDTCON

LFINTOSC Clock

Note 1: This is the shared Timer0/WDT prescaler. See Section 5.4 “Prescaler” for more information.

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