PIC12F683-ISLASHMF datasheet(55/148 Pages) MICROCHIP

55 / 148 page

 2004 Microchip Technology Inc.

Preliminary

DS41211B-page 53

PIC12F683

8.7

Comparator Response Time

Response time is the minimum time, after selecting a

new reference voltage or input source, before the

comparator output is ensured to have a valid level. If

the internal reference is changed, the maximum delay

of the internal voltage reference must be considered

when using the comparator output. Otherwise, the

maximum delay of the comparator should be used

(Table 15-8).

8.8

Operation During Sleep

The comparator and voltage reference, if enabled

before entering Sleep mode, remain active during

Sleep. This results in higher Sleep currents than shown

in the power-down specifications. The additional

current consumed by the comparator and the voltage

reference is shown separately in the specifications. To

minimize power consumption while in Sleep mode, turn

off the comparator, CM<2:0> = 111 and voltage

reference, VRCON<7> = 0.

While the comparator is enabled during Sleep, an inter-

rupt

will

wake-up

the

device.

the

GIE

bit

(INTCON<7>) is set, the device will jump to the inter-

rupt vector (0004h) and if clear, continues execution

with the next instruction. If the device wakes up from

Sleep, the contents of the CMCON0, CMCON1 and

VRCON registers are not affected.

8.9

Effects of a Reset

A device Reset forces the CMCON0, CMCON1 and

VRCON registers to their Reset states. This forces the

comparator module to be in the Comparator Reset

mode, CM<2:0> = 000 and the voltage reference to its

off state. Thus, all potential inputs are analog inputs

with the comparator and voltage reference disabled to

consume the smallest current possible.

VRCON – VOLTAGE REFERENCE CONTROL REGISTER (ADDRESS: 99h)

R/W-0

U-0

R/W-0

VREN

—VRR

—

VR3

VR2

VR1

VR0

bit 7

bit 0

bit 7

VREN: CVREF Enable bit

= CVREF circuit powered on

= CVREF circuit powered down, no IDD drain and CVREF = VSS

bit 6

Unimplemented: Read as ‘0’

bit 5

VRR: CVREF Range Selection bit

= Low range

= High range

bit 4

Unimplemented: Read as ‘0’

bit 3-0

VR<3:0>: CVREF Value Selection 0

≤ VR <3:0> ≤ 15

When VRR = 1: CVREF = (VR<3:0>/24) * VDD

When VRR = 0: CVREF = VDD/4 + (VR<3:0>/32) * VDD

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

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