PIC12F683-ESLASHMF datasheet(82/148 Pages) MICROCHIP

82 / 148 page

PIC12F683

DS41211B-page 80

Preliminary

 2004 Microchip Technology Inc.

12.3.4

BROWN-OUT DETECT (BOD)

The BODEN0 and BODEN1 bits in the Configuration

Word register select one of four BOD modes. Two

modes have been added to allow software or hardware

control of the BOD enable. When BODEN<1:0> = 01,

the SBODEN bit (PCON<4>) enables/disables the

BOD allowing it to be controlled in software. By select-

ing BODEN<1:0>, the BOD is automatically disabled in

Sleep to conserve power and enabled on wake-up. In

this

mode,

the SBODEN

bit

disabled.

See

definition.

If VDD falls below VBOD for greater than parameter

TBOD (see Section 15.0 “Electrical Specifications”),

the Brown-out situation will reset the device. This will

occur regardless of VDD slew rate. A Reset is not

ensured to occur if VDD falls below VBOD for less than

parameter (TBOD).

On any Reset (Power-on, Brown-out Detect, Watchdog

Timer, etc.), the chip will remain in Reset until VDD rises

above VBOD (see Figure 12-3). The Power-up Timer

will now be invoked, if enabled and will keep the chip in

Reset an additional 64 ms.

If VDD drops below VBOD while the Power-up Timer is

running, the chip will go back into a Brown-out Detect

and the Power-up Timer will be re-initialized. Once VDD

rises above VBOD, the Power-up Timer will execute a

64 ms Reset.

12.3.4.1

BOD Calibration

The PIC12F683 stores the BOD calibration values in

fuses located in the Calibration Word register (2008h).

The Calibration Word register is not erased when using

the specified bulk erase sequence in the “PIC12F6XX/

16F6XX

Memory

Programming

Specification”

(DS41204) and thus, does not require reprogramming.

FIGURE 12-3:

BROWN-OUT SITUATIONS

Note:

The Power-up Timer is enabled by the

PWRTE bit in the Configuration Word

Note:

Address

2008h is

beyond the user

program memory space. It belongs to the

special

configuration

memory

space

(2000h-3FFFh), which can be accessed

only

during

programming.

See

“PIC12F6XX/16F6XX Memory Program-

ming Specification” (DS41204) for more

information.

64 ms(1)

VBOD

VDD

Internal

Reset

VBOD

VDD

Internal

Reset

64 ms(1)

< 64 ms

64 ms(1)

VBOD

VDD

Internal

Reset

Note

64 ms delay only if PWRTE bit is programmed to ‘0’.

VBOD

PIC12F683-E/MF Arkusz danych(PDF) 82 Page - Microchip Technology

PIC12F683-E/MF Arkusz danych(HTML) 82 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Arkusz danych Pobierz

Link URL