RT3662EB datasheet(21/28 Pages) RICHTEK

21 / 28 page

RT3662EB

is a registered trademark of Richtek Technology Corporation.

DS3662EB-04

August

2019

www.richtek.com

Bit Time

Description

TFN (Telemetry Functionality)

22 : 24

Load Line Slope Trim [2:0]

25 : 26

Offset Trim [1:0]

SVC

SVT

STOP

START

VDDC Current Bits

VDDC Voltage Bits

Voltage and Current

Mode Selection

Bit Time……

Figure 3. Telemetry Bit Definition

PWROK and SVI2 Operation

The PWROK pin is an input pin, which is connected to

the global power good signal from the platform. Logic

high at this pin enables the SVI2 interface, allowing data

transaction between processor and the RT3662EB.

Once the RT3662EB receives a valid SVID code, it

decodes the information from processor to determine

the output target VID. The internal DAC then steps

up/down the reference voltage in a controlled slew rate,

making the output voltage shift to the required new VID.

If the PWROK input goes low during normal operation,

the SVI2 protocol stops running. The RT3662EB

immediately drives SVT high and modifies all output

voltages back to the Boot VID, which is stored in the

internal register right after the controller is enabled. The

controller does not read SVD and SVC inputs after the

loss of PWROK. If the PWROK input goes high again,

the SVI2 protocol resumes running. The RT3662EB

then waits to decode the SVID command from

processor for a new VID and acts as previously

described. The SVI2 protocol is only runs when the

PWROK input goes high after the voltage at the EN pin

goes high.

VID on-the-Fly Transition

After the RT3662EB has received a valid SVID code, it

executes the VID on-the-Fly transition by stepping

up/down the reference voltage of the required controller

channel in a controlled slew rate, hence allowing the

output voltage to ramp up/down to target VID.

During the VID on-the-Fly transition, the RT3662EB will

force CCM operation in high performance mode. If the

controller channel operates in the power-saving mode

prior to the VID on-the-Fly transition, it will change to

high performance mode and implement CCM operation

when the controller implement VID up, and then remain

in high performance mode; if the controller implement

VID down in power-saving mode, it will decay down and

keep in power-saving mode. The voltage at the PGOOD

pin will keep high during the VID on-the-Fly transition.

The RT3662EB send a VOTF complete only at the end

of VID up transition. In the event of receiving a VID off

code, the RT3662EB steps the reference voltage of

required controller channel down to zero, hence making

the required output voltage decrease to zero, and the

voltage at the PGOOD pin will remain high since the

VID code is valid.

Power State Transition

The RT3662EB supports power state transition function

in VDDC VR for the PSI[x]_L command from AMD

processor. The PSI[x]_L bit in the SVI2 protocol controls

the operating mode of the RT3662EB controller

channels. The default operation mode of VDDC VR is

full-phase CCM.

When the VDDC VR is in N phase configuration and

receives PSI0_L = 0 and PSI1_L = 0 or 1, it will entry

1-phase diode emulation mode. When the VDDC VR

receives PSI0_L = 1 and PSI1_L = 0, it remains 1-phase

diode emulation mode. In reverse, the VDDC VR goes

back to N phase operation in CCM upon receiving

PSI0_L = 1 and PSI1_L = 1, see Table 7.

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