 |
Zakładka z wyszukiwarką danych komponentów |
|
|
Zakładka z wyszukiwarką danych komponentów |
|
WM8721 Arkusz danych(PDF) 9 Page - Wolfson Microelectronics plc |
|
|
|||||||||||||||||||||||||||||
WM8721 Arkusz danych(HTML) 9 Page - Wolfson Microelectronics plc |
|
|
9 / 37 page  Production Data WM8721 / WM8721L w PD Rev 4.0 November 2004 9 DIGITAL AUDIO INTERFACE – SLAVE MODE BCLK DACLRC t BCH t BCL t BCY DACDAT t LRSU t DS t LRH t DH Figure 3 Digital Audio Data Timing – Slave Mode Test Conditions AVDD, HPVDD, DVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25 oC, slave mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Audio Data Input Timing Information BCLK cycle time tBCY 50 ns BCLK pulse width high tBCH 20 ns BCLK pulse width low tBCL 20 ns DACLRC set-up time to BCLK rising edge tLRSU 10 ns DACLRC hold time from BCLK rising edge tLRH 10 ns DACDAT set-up time to BCLK rising edge tDS 10 ns DACDAT hold time from BCLK rising edge tDH 10 ns MPU INTERFACE TIMING CSB SCLK SDIN t CSL t DHO t DSU t CSH t SCY t SCH t SCL t SCS LSB t CSS Figure 4 Program Register Input Timing - 3-Wire MPU Interface Timing |
|
Link URL |
| Czy Alldatasheet okazała się pomocna? [ DONATE ] |
O Alldatasheet | Reklama | Kontakt | Polityka prywatności | Link do karty katalogowej | Linki | Lista producentów All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Polish ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
