M25PE40VMP6TG datasheet(59/60 Pages) STMICROELECTRONICS

59 / 60 page

M25PE40

Revision history

59/60

15-Jan-2007

50 MHz frequency added. SO8N package added, VFQFPN and

SO8W package specifications updated (see Section 12: Package

mechanical).

The sectors are further divided up into subsectors (see Table 4:

Memory organization). Important note on page 6 added. Figure 4:

Bus master and memory devices on the SPI bus updated and

explanatory paragraph added. VCC supply voltage and VSS ground

added. Section 4.8: Protection modes modified. Section 8: Reset

added, Reset timings table split into Table 21: Reset conditions and

Table 22: Timings after a Reset Low pulse.

At Power-up the WIP bit is reset (see Section 7: Power-up and

Power-down).

VIO max changed in Table 13: Absolute maximum ratings. End

timing line of tSHQZ moved in Figure 28: Output timing.

products processed in T9HX process added to datasheet:

–WP pin replaces TSL (T7X technology), see Section 2.6: Write

Protect (W) or Top Sector Lock (TSL)

– Write Status Register (WRSR) and SubSector Erase (SSE)

instructions added for T9HX process

– subsector protection granularity removed in T9HX process, still

exists in T7X process

– Table 4: Memory organization updated to show subsectors

– Status Register BP2, BP1, BP0 bits and SRWD bit added.

Small text changes.

23-Jan-2007

T7X process name corrected.

Write Enable Latch (WEL) bit is reset also on completion of the

SubSector Erase, Bulk Erase, Write to Lock Register and Write

Status Register instructions (see Section 6.2: Write Disable

(WRDI)).

Address bit A20 is not Don’t Care (Note 1 modified) in the Sector

Erase (SE) instruction sequence.. SO8N package is only available

in products manufactured in the T9HX process.

Table 27.

Document revision history

Date

Revision

Changes

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