TLC876M, TLC876I, TLC876C

10-BIT 20 MSPS PARALLEL OUTPUT CMOS

ANALOG-TO-DIGITAL CONVERTERS

SLAS140E – JULY 1997 – REVISED OCTOBER 2000

19

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

layout and decoupling

With high-frequency high-resolution converters, the layout and decoupling of the reference is critical. The actual

voltage digitized by the TLC876 is relative to the reference voltages. In Figure 22, for example, the reference

return and the bypass capacitors are connected to the shield of the incoming analog signal. Disturbances in the

ground of the analog input, that are common mode to the REFTF, REFBF, and AIN terminals because of the

common ground, are effectively removed by the TLC876 high common mode rejection. Also, these capacitors

should be connected as close to reference terminals as possible.

between the analog input ground and the reference bypassing points are treated as input signals by the

converter using the reference inputs. Consequently, the reference decoupling capacitors should be connected

to the same physical analog ground point used by the analog input voltage (see the grounding and layout rules

section).

AIN

REFTF

4 V

VN1

4 V

VN2

REFBF

TLC876

Figure 22. Recommended Bypassing for the Reference

clock input

either 5-V or 3.3-V CMOS logic input signal swings with the input threshold for the CLK terminal nominally at

The internal pipelined architecture operates on both rising and falling edges of the input clock. To minimize duty

cycle variations, the recommended logic family to drive the clock input is high-speed or advanced CMOS

(HC/HCT, AC/ACT) logic. CMOS logic provides both symmetrical voltage threshold levels and sufficient rise and

fall times to support 20 MSPS operation.

The power dissipated by the correction logic and output buffers is largely proportional to the clock frequency.

Figure 8 illustrates this tradeoff between clock rates and a reduction in power consumption.

digital inputs and outputs

The digital output format is straight binary. For example, Table 1 shows the output format for voltage levels of

V(REFTS) = 4 V and V(REFBS) = 2 V.

A low power mode feature is provided such that when STBY is high and the clock is disabled, the static power

of the TLC876 drops significantly (see electrical characteristics table).