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SLK2511BPZP Arkusz danych(PDF) 13 Page - DB Lectro Inc |
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SLK2511BPZP Arkusz danych(HTML) 13 Page - DB Lectro Inc |
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13 / 21 page  www.ti.com ELECTRICAL CHARACTERISTICS 0 50 100 150 200 250 40 42 44 46 48 50 52 54 56 58 60 InputDuty-Cycle-% SLK2511B SLLS763B – JANUARY 2007 – REVISED MARCH 2007 over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TTL VIH High-level input voltage 2 3.6 V VIL Low-level input voltage 0.80 V IIH Input high current VDD = MAX, VIN = 2 V 40 µA IIL Input low current VDD = MAX, VIN =0.4 V –40 µA VOH High-level output voltage IOH = –1 mA 2.10 2.3 V VOL Low-level output voltage IOH = 1 mA 0.25 0.5 V CI Input capacitance 4 pF LVDS INPUT SIGNALS VI Input voltage 825 1575 mV Assumes 60% / 40% duty cycle 250 Input differential threshold voltage VID(th) mV See Figure 5 Assumes 55% / 45% duty cycle 200 tr/tf Input transition time 20% to 80% 375 ps CI Input capacitance 3 pF RI Input differential impedance On-chip termination 80 100 120 Ω tsu Input setup time requirement See Figure 8 300 ps th Input hold time requirement See Figure 8 300 ps T(duty) Input clock duty cycle 40% 60% LVDS OUTPUT SIGNALS VOD Output differential voltage 300 800 VOS Output common mode voltage 1070 1375 RL = 100 ±1% mV VOD Change VOD between 1 and 0 25 VOS Change VOS between 1 and 0 25 I(SP), I(SN), Output short circuit current Outputs shorted to ground or shorted together 24 mA I(SPN) Ioff Power-off current VDD = 0 V 10 µA t(cq_min) 100 Clock-output time See Figure 7 ps t(cq_max) 100 tr/tf Output transition time 20% to 80% 100 300 ps Output clock duty cycle 45% 55% Data output to FRAME_SYNC delay 4 7 Bit times (OC-48 = 622.08 MHz, Clock Rates With tr/tf ≤ 500 ps) Figure 5. LVDS Differential Input Voltage vs Input Duty Cycle 13 Submit Documentation Feedback |
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