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WM8728SEDS/R Arkusz danych(PDF) 10 Page - Wolfson Microelectronics plc |
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WM8728SEDS/R Arkusz danych(HTML) 10 Page - Wolfson Microelectronics plc |
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10 / 28 page ![]() WM8728 Production Data w PD Rev 4.2 April 2004 10 MPU 3-WIRE INTERFACE TIMING Figure 4 Program Register Input Timing - 3-Wire Serial Control Mode Test Conditions AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, TA = +25 oC, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Program Register Input Information SCK rising edge to LATI2S rising edge tSCS 40 ns SCK pulse cycle time tSCY 80 ns SCK pulse width low tSCL 20 ns SCK pulse width high tSCH 20 ns SDIDEM to SCK set-up time tDSU 20 ns SCK to SDIDEM hold time tDHO 20 ns LATI2S pulse width low tCSL 20 ns LATI2S pulse width high tCSH 20 ns LATI2S rising to SCK rising tCSS 20 ns CSBIWL to LATI2S set-up time tCSSU 20 ns LATI2S to CSBIWL hold time tCSSH 20 ns |
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