WM8772SEDSSLASHV datasheet(64/73 Pages) WOLFSON

64 / 73 page

WM8772EFT – 32 LEAD TQFP

Production Data

PD Rev 4.2 October 2005

MASTER MODE DACLRC FREQUENCY SELECT

In Master mode the WM8772EFT generates DACLRC and DACBCLK. These clocks are derived

from the master clock and the ratio of DACMCLK to DACLRC is set by DACRATE.

BIT

LABEL

DEFAULT

DESCRIPTION

0001010

Interface Control

8:6

DACRATE [2:0]

010

Master Mode

DACMCLK:DACLRC Ratio

Select:

000: 128fs

001: 192fs

010: 256fs

011: 384fs

100: 512fs

101: 768fs

ADC DIGITAL AUDIO INTERFACE CONTROL REGISTER

Interface format is selected via the ADCFMT[1:0] register bits:

BIT

LABEL

DEFAULT

DESCRIPTION

0001011

Interface Control

1:0

ADCFMT[1:0]

Interface Format Select

00: Right justified mode

01: Left justified mode

10: I

2S mode

11: DSP mode A or B

The ADCIWL[1:0] bits are used to control the input word length.

BIT

LABEL

DEFAULT

DESCRIPTION

0001011

Interface Control

3:2

ADCIWL[1:0]

Input Word Length

00: 16 bit data

01: 20 bit data

10: 24 bit data

11: 32 bit data

Note: 32-bit right justified mode is not supported.

In all modes, the data is signed 2's complement.

ADC MASTER MODE SELECT

Control bit ADCMS selects between audio interface Master and Slave Modes. In Master mode

ADCLRC and ADCBCLK are outputs and are generated by the WM8772EFT. In Slave mode

ADCLRC and ADCBCLK are inputs to WM8772EFT.

BIT

LABEL

DEFAULT

DESCRIPTION

0001011

Interface Control

ADCMS

ADC Audio Interface

Master/Slave Mode Select:

0: Slave mode

1: Master mode

WM8772SEDS/V Arkusz danych(PDF) 64 Page - Wolfson Microelectronics plc

WM8772SEDS/V Arkusz danych(HTML) 64 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73

Arkusz danych Pobierz

Link URL