WM8955BLGECOSLASHV datasheet(35/44 Pages) WOLFSON

35 / 44 page

Production Data

WM8955BL

PD Rev 4.1 February 2007

POWER MANAGEMENT

The WM8955BL has two control registers that allow users to select which functions are active. For

minimum power consumption, unused functions should be disabled. To avoid any pop or click noise,

it is important to enable or disable functions in the correct order (see Applications Information)

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

8:7

VMIDSEL

VMID resistor divider select

00 – VMID disabled

01 – 50k

Ω divider enabled

10 – 500k

Ω divider enabled

11 – 5k

Ω divider enabled (for fast start-up)

R25 (19h)

Power

Manageme

nt (1)

VREF

VREF (necessary for all other functions)

DACL

DAC Left Enable

0=off

1=on

DACR

DAC Right Enable

0=off

1=on

LOUT1

LOUT1 Output Buffer* Enable

0=off

1=on

ROUT1

ROUT1 Output Buffer* Enable

0=off

1=on

LOUT2

LOUT2 Output Buffer* Enable

0=off

1=on

ROUT2

ROUT2 Output Buffer* Enable

0=off

1=on

MOUT

MONOOUT Output Buffer and Mono Mixer

Enable

0=off

1=on

R26 (1Ah)

Power

Manageme

nt (2)

OUT3

OUT3 Output Buffer Enable

0=off

1=on

Note:

* The left mixer is enabled when LOUT1=1 or LOUT2=1. The right mixer is enabled when

ROUT1=1 or ROUT2=1.

Table 26 Power Management

WM8955BLGECO/V Arkusz danych(PDF) 35 Page - Wolfson Microelectronics plc

WM8955BLGECO/V Arkusz danych(HTML) 35 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

Arkusz danych Pobierz

Link URL