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WM8985GEFL/R Arkusz danych(PDF) 29 Page - Wolfson Microelectronics plc |
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WM8985GEFL/R Arkusz danych(HTML) 29 Page - Wolfson Microelectronics plc |
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29 / 118 page ![]() Pre-Production WM8985 w PP, Rev 3.5, January 2007 29 and the non-inverting input of the input PGA clamped to VMID. Figure 12 Microphone Input PGA Circuit The input PGAs are enabled by the INPPGAENL and INPPGAENR register bits. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 2 INPPGAENL 0 Left channel input PGA enable 0 = disabled 1 = enabled R2 (02h) Power Management 2 3 INPPGAENR 0 Right channel input PGA enable 0 = disabled 1 = enabled Table 5 Input PGA Enable Register Settings |
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