AT43USB326 datasheet(7/102 Pages) ATMEL

7 / 102 page

AT43USB326

3313D–USB–04/06

instruction is being executed, the next instruction is pre-fetched from the program memory.

This concept enables instructions to be executed in every clock cycle. The program memory is

a downloadable SRAM or a mask programmed ROM.

With the relative jump and call instructions, the whole 24K address space is directly accessed.

Most AVR instructions have a single 16-bit word format. Every program memory address con-

tains a 16- or 32-bit instruction.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on

the stack. The stack is effectively allocated in the general data SRAM, and consequently, the

stack size is only limited by the total SRAM size and the usage of the SRAM. All user pro-

grams must initialize the Stack Pointer (SP) in the reset routine (before subroutines or

interrupts are executed). The 10-bit SP is read/write accessible in the I/O space.

The 1-Kbyte data SRAM can be easily accessed through the five different addressing modes

supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps. A flexi-

ble interrupt module has its control registers in the I/O space with an additional global interrupt

enable bit in the status register. All interrupts have a separate interrupt vector in the interrupt

vector table at the beginning of the program memory. The interrupts have priority in accor-

dance with their interrupt vector position. The lower the interrupt vector address, the higher the

priority.

The General-

purpose

All register operating instructions in the instruction set have direct and single cycle access to

all registers. The only exception is the five constant arithmetic and logic instructions SBCI,

SUBI, CPI, ANDI, and ORI between a constant and a register, and the LDI instruction for load

Table 1. AVR CPU General-purpose Working Register

Address

Comment

$00

$01

$02

R13

$0D

R14

$0E

R15

$0F

R16

$10

R17

$11

R26

$1A

X-register low byte

R27

$1B

X-register high byte

R28

$1C

Y-register low byte

R29

$1D

Y-register high byte

R30

$1E

Z-register low byte

R31

$1F

Z-register high byte

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