ST7538Q datasheet(24/44 Pages) STMICROELECTRONICS

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Functional description

ST7538Q

24/44

Figure 10. ST7538Q PLL lock-in range

5.7.3

Carrier/preamble detection

The Carrier/Preamble Block is a digital Frequency detector Circuit.

It can be used to manage the MAINS access and to detect an incoming signal.

Two are the possible setting:

●

Carrier detection: The Carrier/Preamble detection Block notifies to the host controller

the presence of a Carrier when it detects on the RAI Input a signal with an harmonic

component close to the programmed Carrier Frequency. The CD_PD signal sensitivity

is identical to the data reception sensitivity (0.5mVrms Typ. in Normal Sensitivity

Mode).

The CD_PD line is forced to a logic level low when a Carrier is detected.

●

Preamble detection: The Carrier/Preamble detection Block notifies to the host

controller the presence of a Carrier modulated at the Programmed Baud Rate for at

least 4 Consecutive Symbols (“1010” or “0101” are the symbols sequences detected).

CD_PD line is forced low till a Carrier signal is detected and PLL is in the lock-in range.

To reinforce the effectiveness of the information given by CD_PD Block, a digital

filtering is applied on Carrier or Preamble notification signal (See Control Register

Paragraph). The Detection Time Bits in the Control Register define the filter

performance. Increasing the Detection Time reduces the false notifications caused by

noise on main line. The Digital filter adds a delay to CD_PD notification equal to the

programmed Detection Time. When the carrier frequency disappears, CD_PD line is

held low for a period equal to the detection time and then forced high. During this time

the some spurious data caused by noise can be demodulated.

5.7.4

Header recognition

In Extended Control Register Mode (Control Register bit 21 = ”1”, see Table 11) the CD_PD

line can be used to recognize if an header has been sent during the transmission. With

Header Recognition function enable (Control Register bit 18 = ”1”, see Table 11), CD_PD

line is forced low when a Frame Header is detected. If Frame Length Count function is

enabled, CD_PD is held low and a number of 16 bit word equal to the Frame Length

selected is sent to the host controller. In this case, CLR/T is forced to “0” and RxD is forced

to “0” or “1” (according the UART/SPI pin level) when Header has not been detected or after

the Frame Length has been reached.

If Frame Length Count function is disabled, an header recognition is signaled by forcing

CD_PD low for one period of CLR/T line. In this case, CLR/T and RxD signal are always

present, even if no header has been recognized.

CLR/T

RxD

D03IN1417

LOCK-IN RANGE

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