PCF8531USLASH2 datasheet(24/44 Pages) PHILIPS

24 / 44 page

2000 Feb 11

Philips Semiconductors

Product speciﬁcation

× 128 pixel matrix driver

PCF8531

13 AC CHARACTERISTICS

VDD1 = 1.8 to 5.5 V; VDD2 and VDD3 = 2.5 to 4.5 V; VSS1 and VSS2 =0V; VDD1 to VDD3 ≤ VLCD ≤ 9.0 V;

Tamb = −40 to +85 °C; unless otherwise speciﬁed.

Notes

1. fframe =fclk(ext)/480; fOSC/480.

2. For tW(RESL) > 3 ns a reset may be generated.

3. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to

VIL and VIH with an input voltage swing of VSS to VDD.

4. Cb = total capacitance of one bus line in pF.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

fframe

LCD frame frequency (internal clock)

VDD = 3.0 V; note 1 40

135

fOSC

oscillator frequency (not available at any pin)

kHz

fclk(ext)

external clock frequency

−

kHz

tW(RESL)

reset LOW pulse width

note 2

300

−−

tSU;RESL

reset LOW pulse set-up time after Power-on

−−

µs

Serial-bus interface; note 3

fSCL

SCL clock frequency

−

400

kHz

tSCLL

SCL clock LOW period

1.3

−−µs

tSCLH

SCL clock HIGH period

0.6

−−µs

tSU;DAT

data set-up time

100

−−

tHD;DAT

data hold time

−

0.9

µs

SCL, SDA rise time

note 4

20 + 0.1Cb

−

300

SCL, SDA fall time

note 4

20 + 0.1Cb

−

300

capacitive load represented by each bus line

−−

400

tSU;STA

set-up time for a repeated START condition

0.6

−−µs

tHD;STA

start condition hold time

0.6

−−µs

tSU;STO

set-up time for STOP condition

0.6

−−µs

tSW

tolerable spike width on bus

−−

tBUF

bus free time between a STOP and START

condition

1.3

−−µs

handbook, full pagewidth

MGS476

tW(RESL)

tSU;RESL

VIL

VDD

RES

Fig.16 Reset timing.

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