PCF8575 datasheet(15/24 Pages) PHILIPS

15 / 24 page

1999 Apr 07

Philips Semiconductors

Product speciﬁcation

Remote 16-bit I/O expander for I2C-bus

PCF8575

11 I2C-BUS TIMING CHARACTERISTICS

See Fig.13 and note 1.

Notes

1. All the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL

and VIH with an input voltage swing of VSS to VDD.

2. The device inputs SDA and SCL are filtered and will reject spikes on the bus lines of widths less than tSW(max).

3. The rise and fall times specified here refer to the driver device (PCF8575) and are part of the general fast I2C-bus

specification when PCF8575 asserts an acknowledge on SDA, the minimum fall time is 20 ns + 0.1Cb.

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

fSCL

SCL clock frequency

−

400

kHz

tSW

tolerable spike width on bus

note 2

−

tBUF

BUS free time between a STOP

and START condition

1.3

−µs

tSU;STA

START condition set-up time

0.6

−µs

tHD;STA

START condition hold time

0.6

−µs

tLOW

SCL LOW time

1.3

−µs

tHIGH

SCL HIGH time

0.6

−µs

SCL and SDA rise time

note 3

20 + 0.1Cb

300

SCL and SDA fall time

note 3

20 + 0.1Cb

300

tSU;DAT

data set-up time

100

−

tHD;DAT

data hold time

−

tSU;STO

STOP condition set-up time

0.6

−µs

capacitive load represented by

each bus line

−

400

Fig.13 I2C-bus timing diagram.

handbook, full pagewidth

PROTOCOL

SCL

SDA

MGL546

BIT 0

LSB

(R/W)

tSU;STA

tSU;DAT

tSU;STO

tHD;STA

tHD;DAT

tBUF

tLOW

tHIGH

1/fSCL

START

CONDITION

(S)

BIT 7

MSB

(A7)

BIT 6

(A6)

ACKNOWLEDGE

(A)

STOP

CONDITION

(P)

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