34717 datasheet(21/25 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

34717

TYPICAL APPLICATIONS

OPERATIONAL MODES

resistors will affect the accuracy of the system and must be

1% accurate resistors.

To achieve this tracking configuration, the master voltage

must be connected in the way shown and cannot be directly

connected to the VREFIN terminal.

Figure 12. Ratiometric Tracking Circuit Connections

EQUATIONS

•VM = VBG_M(1+R3/R4)

•VREFIN = VM * R4/(R3+R4)

•VREFOUT = VREFIN

•VS = VREFOUT(1+R1/R2) = VM* R4/(R3+R4)*(R2+R1)/R2,

if VREFOUT < VBG_S

•VS = VBG_S(1+R1/R2), if VREFOUT ≥ VBG_S

Figure 13. Ratiometric Tracking Plot

CO-INCIDENTAL TRACKING CIRCUIT

CONFIGURATION:

Connect a three resistor divider to the master voltage (VM)

and Route the upper tap point of the divider to the VREFIN

terminal, resistors R3, R4, and R5 as shown in Figure 14. This

resistor divider must be the same ratio as the slave output’s

(VS) feedback resistor divider, which in turn connects to the

INV- terminal, resistors R1 and R2 below (Condition: R1 = R3

and R2 = R4 + R5). The master’s feedback resistor divider

would be (R3+R4) and R5. All five resistors will affect the

accuracy of the system and must be 1% accurate resistors.

To achieve this tracking configuration, the master voltage

must be connected in the way shown and cannot be directly

connected to the VREFIN terminal.

Figure 14. Co-incidental Tracking Circuit Connections

EQUATIONS

•VM = VBG_M[1+(R3+R4)/R5]

•VREFIN = VM*(R4+R5)/(R3+R4+R5)

•VREFOUT = VREFIN

•VS = VREFOUT(1+R1/R2) = VM*(R4+R5)/

(R3+R4+R5)*(R2+R1)/R2 = VM if VREFOUT < VBG_S

•VS = VBG_S(1+R1/R2), if VREFOUT ≥ VBG_S

Figure 15. Co-incidental Tracking Plot

Not-DDR Mode (Source Only Mode) is the case when no

tracking is needed. VREFIN should be connected to VDDI

and the reference selection block will use the internal band

gap voltage as the error amplifier’s reference voltage.

A user can potentially apply a voltage to the VREFIN

terminal directly or through a resistor divider to get a buffered

output for use in the application. The condition here is, the

voltage applied to the VREFIN terminal is greater than VBG to

guarantee that the reference selection block will not switch

back to the VREFOUT voltage.

VSLAVE

INV

COMP

VREFIN

Reference

selector

VBG

VMASTER

To INV- of

Vmaster

VSLAVE

INV

COMP

VREFIN

Reference

selector

VBG

VMASTER

To INV- of

Vmaster

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