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AD5522JSVD Arkusz danych(PDF) 41 Page - Analog Devices

Numer części AD5522JSVD
Szczegółowy opis  Quad Parametric Measurement Unit With Integrated 16-Bit Level Setting DACs
PDF  48 Pages
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AD5522JSVD Arkusz danych(HTML) 41 Page - Analog Devices

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Preliminary Technical Data
AD5522
Rev. PrM | Page 41 of 48
POWER ON DEFAULT
The power on default for all DAC channels is that the contents of each m register is set to full-scale (0xFFFF) and c register to
midscale(0x8000). The contents of the DAC registers are :
Offset DAC: 0xA492, FIN DACs: 0x8000, CLL DACs: 0x0000, CLH DACs: 0xFFFF, CPL DACs: 0x0000, CPH DACs: 0xFFFF
The power on default for the Alarm Status Register is 0xFFFFF0, while the Comparator Status registers powers up at 0x400000. The
power on defaults of the PMU register and the System Control Register are shown below.
Table 28. Power on Default for System Control Register and PMU Register
SYSTEM CONTROL REGISTER POWER ON DEFAULT
PMU REGISTER POWER ON DEFAULT
Bit
Bit name
Description
Bit name
Description
21 (MSB)
CL3
0
CH EN
0
20
CL2
0
FORCE1
0
19
CL1
0
FORCE0
0
18
CL0
0
RESERVED
0
17
CPOLH3
0
C2
0
16
CPOLH2
0
C1
1
15
CPOLH1
0
C0
1
14
CPOLH0
0
MEAS1
1
13
CPBIASEN
0
MEAS0
1
12
DUTGND/CH
0
FIN
0
11
GUARD ALM
0
SFO
0
10
CLAMP ALM
0
SSO
0
9
INT10K
0
CL
0
8
GUARD EN
0
CPOLH
0
7
GAIN1
0
COMPARE V/I
0
6
GAIN0
0
LTMPALM
1
5
TMP ENABLE
1
TMPALM
1
4
TMP1
0
0
3
TMP0
0
0
2
LATCHED
0
0
1
0
0
0 (LSB)
Unused Data Bits
0
Unused Data Bits
0



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