PHT6N03LT datasheet(3/6 Pages) PHILIPS

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Philips Semiconductors

Product specification

TrenchMOS

™ transistor

PHT6N03LT

Logic level FET

AVALANCHE LIMITING VALUE

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

DSS

Drain-source non-repetitive

D = 5.9 A; VDD ≤ 15 V;

unclamped inductive turn-off

GS = 10 V; RGS = 50 Ω; Tamb = 25 ˚C

energy

Fig.1. Normalised power dissipation.

PD% = 100

⋅P

D/PD 25 ˚C = f(Tamb)

Fig.2. Normalised continuous drain current.

ID% = 100

⋅I

D/ID 25 ˚C = f(Tamb); conditions: VGS ≥ 5 V

Fig.3. Safe operating area. T

amb = 25 ˚C

D & IDM = f(VDS); IDM single pulse; parameter tp

Fig.4. Transient thermal impedance.

th j-amb = f(t); parameter D = tp/T

100

120

140

Tamb / C

PD%

Normalised Power Derating

120

110

100

0.1

100

1000

0.01

0.1

100

7830-30

VDS / V

ID / A

RDS(ON)

VDS

/ ID

tp = 10 us

100 us

1 ms

10 ms

100 ms

100

120

140

Ambient temperature, Tamb (C)

ID%

Normalised Current Derating

120

110

100

1E-07

1E-05

1E-03

1E-01

1E+01

1E+03

BUKX83

t / s

Zth j-amb / (K/W)

1E+02

1E+01

1E+00

1E-01

1E-02

0.5

0.2

0.1

0.05

0.02

D =

January 1998

Rev 1.300

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