LR4102 datasheet(11/32 Pages) LSI

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TinyRISC LR4102 Microprocessor

LR4102 Register Map

Table 4 shows the LR4102 microprocessor register memory map.

Table 4

LR4102 Register Memory Map

Physical Address

Description

System conﬁguration registers in BBCC

SCR1

0x1FFF.0000

System Conﬁguration Register 1

SCR2

0x1FFF.0004

System Conﬁguration Register 2

SCR3

0x1FFF.0008

System Conﬁguration Register 3

Timer registers

T0ICR

0x1FFF.0100

Timer 0 Initial Count Register

T0CCR

0x1FFF.0104

Timer 0 Current Count Register

T1ICR

0x1FFF.0108

Timer 1 Initial Count Register

T1CCR

0x1FFF.010C

Timer 1 Current Count Register

TMR

0x1FFF.0110

Mode Register

TISR

0x1FFF.0114

Interrupt Status Register

SerialICE-1 Port (UART) registers

RxStatus

0x1FFF.0200

Receive (Rx) Status Register (Reading)

RxSetup

0x1FFF.0200

Receive (Rx) Setup Register (Writing)

RxData

0x1FFF.0204

Receive (Rx) Data Register

TxStatus

0x1FFF.0208

Transmit (Tx) Status Register

TxData

0x1FFF.020C

Transmit (Tx) Data Register

Reserved registers

Reserved

0x1FFF.0300–.03FF

Reserved for LSI Logic use

FBus registers

FACFG0

0x1FFF.0400

Conﬁguration for address range 0

FACFG1

0x1FFF.0404

Conﬁguration for address range 1

(Sheet 1 of 2)

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