56F8367 datasheet(19/184 Pages) FREESCALE

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Signal Pins

56F8367 Technical Data, Rev. 8

Freescale Semiconductor

Preliminary

VSS

Supply

VSS — These pins provide ground for chip logic and I/O drivers.

VSS

K11

VSS

G11

VSS

125

J11

VSS

160

VSSA_ADC

115

D12

Supply

ADC Analog Ground — This pin supplies an analog ground to

the ADC modules.

OCR_DIS

K14

Input

On-Chip Regulator Disable —

Tie this pin to VSS to enable the on-chip regulator

Tie this pin to VDD to disable the on-chip regulator

This pin is intended to be a static DC signal from power-up to

shut down. Do not try to toggle this pin for power savings

during operation.

VCAP1*

Supply

VCAP1 - 4 — When OCR_DIS is tied to VSS (regulator enabled),

connect each pin to a 2.2

μF or greater bypass capacitor in order

to bypass the core logic voltage regulator, required for proper chip

operation. When OCR_DIS is tied to VDD (regulator disabled),

these pins become VDD_CORE and should be connected to a

regulated 2.5V power supply.

Note: This bypass is required even if the chip is powered

with an external supply.

VCAP2*

144

VCAP3*

H11

VCAP4*

* When the on-chip regulator is disabled, these four pins become 2.5V VDD_CORE.

VPP1

141

Input

VPP1 - 2 — These pins should be left unconnected as an open

circuit for normal functionality.

VPP2

2C2

CLKMODE

H12

Input

Clock Input Mode Selection — This input determines the

function of the XTAL and EXTAL pins.

1 = External clock input on XTAL is used to directly drive the input

clock of the chip. The EXTAL pin should be grounded.

0 = A crystal or ceramic resonator should be connected between

XTAL and EXTAL.

EXTAL

J12

Input

External Crystal Oscillator Input — This input can be

connected to an 8MHz external crystal. Tie this pin low if XTAL is

driven by an external clock source.

Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued)

Signal

Name

No.

Ball No.

Type

State

During

Reset

Signal Description

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