RF112 datasheet(4/45 Pages) NXP

4 / 45 page

gain in receive mode should be controlled by the baseband IC. The receive chain has low

noise and high dynamic range. The analog baseband filters have on-chip calibration and

supports 20, 40, or 80 MHz modulation bandwidth. An internal crystal oscillator is

implemented to enable usage of a low cost crystal. The reference frequency can be fine-

tuned to minimize the frequency error. A LVDS clock output is included to provide a

reference clock to the baseband chip. An auxiliary ADC is implemented for calibration

purposes and to serve various external functions like power and temperature

measurements.

The two interfaces, a traditional low-speed I2C, and a low complexity high-speed custom

LVDS buses are available for configuration and bi-directional data exchanges with the

baseband. The high-speed LLCP interface can be used to provide a continuous stream of

RF envelope detector samples after the LNA in each receiver chain. This allows the

receiver AGC algorithm, located on the baseband chip, to observe the wideband signal

level and optimize the receiver gain for best performance. The interface allows quick

updates of the transmitter and receiver gains.

This figure shows top level block diagram of the RF112 Transceiver.

Introduction

RF112 Transceiver Data Sheet, Rev. 1 Draft B, 05/2024

NXP Semiconductors

RF112 Arkusz danych(PDF) 4 Page - NXP Semiconductors