SL2S3103FUD datasheet(8/80 Pages) NXP

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NXP Semiconductors

SL2S3103

ICODE 3 97pF

7 Mechanical specification

7.1 Wafer specification

Refer to [5].

Parameter

Value

Wafer

Designation

each wafer is enscribed with batch number and wafer number

Diameter

300 mm (12 inches)

Thickness

120 μm ± 15 μm

Process

CMOS 0.14 μm

Batch size

25 wafers

Dies per wafer

140037

Wafer backside

Material

Treatment

ground and stress release

Ra minimum = 0.5 μm

Roughness

Rt maximum = 5 μm

Chip dimensions

Die size without scribe

640 μm × 660 μm = 0.4224 mm2

Scribe line width

X-dimension

35 μm (scribe line width measured between nitride edges)

Y-dimension

35 μm (scribe line width measured between nitride edges)

Number of pads

Pad location

non-diagonal/placed in chip corners

Distance pad to pad LA to LB

530 μm (center to center)

Distance pad to pad LB to TP

550 μm (center to center)

Passivation on front

Type

sandwich structure

Material

PE-nitride (on top)

Thickness

1.75 μm total thickness of passivation

Au bump

Material

>99.9 % pure Au

Hardness

35 HV to 80 HV 0.005

Shear strength

>70 MPa

Height

18 μm

Table 3. Wafer specification

SL2S3103

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3.1 — 29 May 2024

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