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MPC855T Arkusz danych(PDF) 60 Page - Freescale Semiconductor, Inc |
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MPC855T Arkusz danych(HTML) 60 Page - Freescale Semiconductor, Inc |
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60 / 80 page ![]() MPC860 Family Hardware Specifications, Rev. 7 60 Freescale Semiconductor CPM Electrical Characteristics Figure 60. Ethernet Transmit Timing Diagram Figure 61. CAM Interface Receive Start Timing Diagram Figure 62. CAM Interface REJECT Timing Diagram TCLK1 128 TxD1 (Output) 128 TENA(RTS1) (Input) NOTES: Transmit clock invert (TCI) bit in GSMR is set. If RENA is deasserted before TENA, or RENA is not asserted at all during transmit, then the CSL bit is set in the buffer descriptor at the end of the frame transmission. 1. 2. RENA(CD1) (Input) 133 134 132 131 121 129 (NOTE 2) RCLK1 RxD1 (Input) RSTRT (Output) 0 136 125 1 1 BIT1 BIT2 Start Frame De- REJECT 137 |
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