MPC862 datasheet(71/88 Pages) FREESCALE

71 / 88 page

MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3

Freescale Semiconductor

FEC Electrical Characteristics

Figure 74 shows the MII transmit signal timing diagram.

Figure 74. MII Transmit Signal Timing Diagram

13.3

MII Async Inputs Signal Timing (MII_CRS, MII_COL)

Table 31 provides information on the MII async inputs signal timing.

Figure 75 shows the MII asynchronous inputs signal timing diagram.

Figure 75. MII Async Inputs Timing Diagram

13.4

MII Serial Management Channel Timing (MII_MDIO, MII_MDC)

Table 32 provides information on the MII serial management channel signal timing. The FEC functions

correctly with a maximum MDC frequency in excess of 2.5 MHz. The exact upper bound is under

investigation.

MII_TX_CLK pulse width high

35%

65%

MII_TX_CLK period

MII_TX_CLK pulse width low

35%

65%

MII_TX_CLK period

Table 31. MII Async Inputs Signal Timing

Num

Characteristic

Min

Max

Unit

MII_CRS, MII_COL minimum pulse width

1.5

—

MII_TX_CLK period

Table 30. MII Transmit Signal Timing (continued)

Num

Characteristic

Min

Max

Unit

MII_TX_CLK (input)

MII_TXD[3:0] (outputs)

MII_TX_EN

MII_TX_ER

MII_CRS, MII_COL

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