MPC866 datasheet(76/96 Pages) FREESCALE

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MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor

FEC Electrical Characteristics

Figure 75 shows the MII transmit signal timing diagram.

Figure 75. MII Transmit Signal Timing Diagram

14.3 MII Async Inputs Signal Timing (MII_CRS, MII_COL)

Table 35 shows the timing for on the MII async inputs signal.

Figure 76 shows the MII asynchronous inputs signal timing diagram.

Figure 76. MII Async Inputs Timing Diagram

14.4 MII Serial Management Channel Timing (MII_MDIO, MII_MDC)

Table 36 shows the timing for the MII serial management channel signal. The FEC functions correctly with a

maximum MDC frequency in excess of 2.5 MHz. The exact upper bound is under investigation.

Table 35. MII Async Inputs Signal Timing

Num

Characteristic

Min

Max

Unit

MII_CRS, MII_COL minimum pulse width

1.5

—

MII_TX_CLK period

Table 36. MII Serial Management Channel Timing

Num

Characteristic

Min

Max

Unit

M10

MII_MDC falling edge to MII_MDIO output invalid (minimum

propagation delay)

0—

M11

MII_MDC falling edge to MII_MDIO output valid (maximum

propagation delay)

—25

M12

MII_MDIO (input) to MII_MDC rising edge setup

—

MII_TX_CLK (input)

MII_TXD[3:0] (outputs)

MII_TX_EN

MII_TX_ER

MII_CRS, MII_COL

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