MPC8280CVRM datasheet(24/80 Pages) FREESCALE

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MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

Freescale Semiconductor

Clock Configuration Modes

The MPC8280 has three clocking modes: local, PCI host, and PCI agent. The clocking mode is set according to three

input pins—PCI_MODE, PCI_CFG[0], PCI_MODCK—as shown in Table 15.

Input hold times

Boundary-scan data

TMS, TDI

tJTDXKH

tJTIXKH

—

4, 7

Output valid times

Boundary-scan data

TDO

tJTKLDV

tJTKLOV

—

5, 7

5. 7

Output hold times

Boundary-scan data

TDO

tJTKLDX

tJTKLOX

—

5, 7

JTAG external clock to output high impedance

Boundary-scan data

TDO

tJTKLDZ

tJTKLOZ

5, 6

1 All outputs are measured from the midpoint voltage of the falling/rising edge of t

TCLK to the midpoint of the signal

in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-

Ω load.

Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.

2 The symbols used for timing specifications herein follow the pattern of t

(first two letters of functional block)(signal)(state)

(reference)(state) for inputs and t((first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,

tJTDVKH symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state

(V) relative to the tJTG clock reference (K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG

timing (JT) with respect to the time data input signals (D) went invalid (X) relative to the tJTG clock reference (K)

going to the high (H) state. Note that, in general, the clock reference symbol representation is based on three letters

representing the clock of a particular functional. For rise and fall times, the latter convention is used with the

appropriate letter: R (rise) or F (fall).

3 TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.

4 Non-JTAG signal input timing with respect to t

TCLK.

5 Non-JTAG signal output timing with respect to t

TCLK.

6 Guaranteed by design.

7 Guaranteed by design and device characterization.

Table 15. MPC8280 Clocking Modes

Pins

Clocking Mode

PCI Clock

Frequency Range

(MHZ)

Reference

PCI_MODE

PCI_CFG[0] PCI_MODCK1

Determines PCI clock frequency range. Refer to Sections 7.2 and 7.3.

—

Local bus

—

Table 16

PCI host

50–66

Table 17

25–50

Table 18

PCI agent

50–66

Table 19

25–50

Table 20

Table 14. JTAG Timings1 (continued)

Parameter

Symbol2

Min

Max

Unit

Notes

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