13 / 50 page  - 13 - © Andigilog, Inc. 2006 www.andigilog.com October 2006 - 70A06010 aSC7621 R/W Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) De- fault Value (hex) 28h R Tach 1 LS Byte 7 6 5 4 3 2 1 0 FF 29h R Tach 1 MS Byte 15 14 13 12 11 10 9 8 FF 2Ah R Tach 2 LS Byte 7 6 5 4 3 2 1 0 FF 2Bh R Tach 2 MS Byte 15 14 13 12 11 10 9 8 FF 2Ch R Tach 3 LS Byte 7 6 5 4 3 2 1 0 FF 2Dh R Tach 3 MS Byte 15 14 13 12 11 10 9 8 FF 2Eh R Tach 4 LS Byte 7 6 5 4 3 2 1 0 FF 2Fh R Tach 4 MS Byte 15 14 13 12 11 10 9 8 FF 30h R/W Fan 1 Current PWM Duty 7 6 5 4 3 2 1 0 FF 31h R/W Fan 2 Current PWM Duty 7 6 5 4 3 2 1 0 FF 32h R/W Fan 3 Current PWM Duty 7 6 5 4 3 2 1 0 FF 33h R Zone 4 Temperature (MS Byte) 9 8 7 6 5 4 3 2 N/A 34h R/W Zone 4 Low Temp 7 6 5 4 3 2 1 0 81h 35h R/W Zone 4 High Temp 7 6 5 4 3 2 1 0 00h 36h R/W PECI Configuration RES RES RES LEG DOM AVG2 AVG1 AVG0 00h X 38h R/W Fan 1 Max Duty Cycle 7 6 5 4 3 2 1 0 FF X 39h R/W Fan 2 Max Duty Cycle 7 6 5 4 3 2 1 0 FF X 3Ah R/W Fan 3 Max Duty Cycle 7 6 5 4 3 2 1 0 FF X 3Bh R/W Zone 4 Fan Temp Limit 7 6 5 4 3 2 1 0 E0h X 3Ch R/W Zone 4 Range, Spike Smoothing RAN3 RAN2 RAN1 RAN0 ZN4E ZN4-2 ZN4-1 ZN4-0 C3h X 3Dh R/W Zone 4 Absolute Temp Limit 7 6 5 4 3 2 1 0 00h X 3Eh R Company ID 7 6 5 4 3 2 1 0 61 3Fh R Version/ Stepping VER3 VER2 VER1 VER0 4WIRE PECI STP1 STP0 6C 40h R/W Ready/Lock/ Start/Override RES RES SAFE PECI OVRID READY LOCK START 00 X 2 41h R Interrupt Status Register 1 ERR ZN3 ZN2 ZN1 5V 3.3V VCCP 2.5V 00 42h R Interrupt Status Register 2 ERR2 ERR1 FAN4 FAN3 FAN2 FAN1 ERR 12V 00 43h R Interrupt Status Register 3 ERR RES RES RES ALOVR COMM DATA ZN4 00h |
|
Polish ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
