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SC2000 Arkusz danych(PDF) 36 Page - NXP Semiconductors

Numer części SC2000
Szczegółowy opis  Universal Timeslot Interchange
PDF  44 Pages
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Producent  PHILIPS [NXP Semiconductors]
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SC2000 Arkusz danych(HTML) 36 Page - NXP Semiconductors

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2000 Sep 07
36
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC2000
Table 13. CLK_IN, SYNC_IN — PEB Network Master Mode (CLK_IN Divider
≥ 2)
Symbol
Parameter
Min
Typ
Max
Unit
t1
CLK_IN period
244
ns
t2
CLK_IN high time
122
ns
t3
CLK_IN low time
122
ns
t4
SYNC_IN low setup to CLK_IN
↓(PEB conventional)
10
ns
t5
SYNC_IN low hold from CLK_IN
↓(PEB conventional)
10
ns
t6
SYNC_IN high setup to CLK_IN
↓(PEB conventional)
10
ns
t7
SYNC_IN high hold from CLK_IN
↓(PEB conventional)
10
ns
t8
SYNC_IN setup to CLK_IN
↓ (ST-BUS)
10
ns
t9
SYNC_IN hold from CLK_IN
↓ (ST-BUS)
10
ns
t10a
CLKR, L_CLKT
↑delay from CLK_IN↑(PEB conventional)
60
ns
t10b
CLKR, L_CLKT
↑delay from CLK_IN↓ (ST-BUS)
60
ns
t11a
CLKR, L_CLKT
↓delay from CLK_IN ↑(PEB conventional)
30
ns
t11b
CLKR, L_CLKT
↓delay from CLK_IN↓ (ST-BUS)
30
ns
t12
FSYNCR, L_FSYNCT
↑delay from CLKR↑
70
ns
t13
FSYNCR, L_FSYNCT
↓delay from CLKR↑
35
ns
t14
MSYNCR
↑delay from CLKR↑
70
ns
t15
MSYNCR
↓delay from CLKR↑
35
ns
t16
L_MSYNCT
↑delay from CLKR↑
70
ns
t17
L_MSYNCT
↓delay from CLKR↑
35
ns
t18
L_MSYNCT
↑delay from MSYNCT↑
60
ns
t19
L_MSYNCT
↓delay from MSYNCT↓
25
ns
Note:
1. Timing measured with 200 pF 220/330
Ωtermination on all PEB outputs. Open collector low to high transitions include 43 ns delay from hi-Z to 2.4 V.



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