24FC65T-SLASHP datasheet(7/14 Pages) MICROCHIP

7 / 14 page

 2004 Microchip Technology Inc.

DS21125E-page 7

24FC65

5.0

READ OPERATION

Read operations are initiated in the same way as write

operations with the exception that the R/W bit of the

slave address is set to one. There are three basic

types of read operations: current address read, random

read, and sequential read.

5.1

Current Address Read

The 24FC65 contains an address counter that

maintains the address of the last word accessed,

internally incremented by one. Therefore, if the

previous access (either a read or write operation) was

to address n (n is any legal address), the next current

address read operation would access data from

address n + 1. Upon receipt of the slave address with

R/W bit set to one, the 24FC65 issues an acknowledge

and transmits the eight bit data word. The master will

not acknowledge the transfer but does generate a

STOP and the 24FC65 discontinues transmission

(Figure 4-3).

5.2

Random Read

Random read operations allow the master to access

any memory location in a random manner. To perform

this type of read operation, first the word address must

be set. This is done by sending the word address to the

24FC65 as part of a write operation (R/W bit set to 0).

After the word address is sent, the master generates a

START following the acknowledge. This terminates the

write operation, but not before the internal address

pointer is set. Then the master issues the control byte

again but with the R/W bit set to a one. The 24FC65 will

then issue an acknowledge and transmit the eight bit

data word. The master will not acknowledge the

transfer but does generate a STOP which causes the

24FC65 to discontinue transmission (Figure 4-4).

5.3

Sequential Read

Sequential reads are initiated in the same way as a

random read except that after the 24FC65 transmits

the first data byte, the master issues an acknowledge

as opposed to the STOP used in a random read. This

acknowledge directs the 24FC65 to transmit the next

sequentially

addressed

bit

word

(Figure 4-5).

Following the final byte transmitted to the master, the

master will NOT generate an acknowledge but will

generate a STOP.

To provide sequential reads the 24FC65 contains an

internal address pointer which is incremented by one at

the completion of each operation. This address pointer

allows the entire memory contents to be serially read

during one operation.

5.4

Contiguous Addressing Across

Multiple Devices

The device select bits A2, A1, A0 can be used to

expand the contiguous address space for up to

512K-bits by adding up to eight 24FC65's on the same

bus. In this case, software can use A0 of the control

byte as address bit A13, A1 as address bit A14, and A2

as address bit A15.

5.5

Noise Protection

The SCL and SDA inputs incorporate Schmitt triggers

which suppress noise spikes to assure proper device

operation even on a noisy bus.

5.6

High Endurance Block

The location of the high-endurance block within the

memory map is programmed by setting the leading bit

7 (S/HE) of the configuration byte to 0. The upper bits

of the address loaded in this command will determine

which 4K block within the memory map will be set to

high endurance (Figure 8-1). This block will be capable

of 10,000,000 erase/write cycles guaranteed.

5.7

Security Options

The 24FC65 has a sophisticated mechanism for

write-protecting portions of the array. This write protect

function is programmable and allows the user to protect

0-15 contiguous 4K blocks. The user sets the security

option by sending to the device the starting block num-

ber for the protected region and the number of blocks

to be protected. All parts will come from the factory in

the default configuration with the starting block number

set to 15 and the number of protected blocks set to

zero. THE SECURITY OPTION CAN BE SET ONLY

ONCE.

To invoke the security option, a write command is sent

to the device with the leading bit (bit7) of the first

address byte set to a 1 (Figure 8-1). Bits 1-4 of the first

address byte define the starting block number for the

protected region. For example, if the starting block

number is to be set to 5, the first address byte would be

1XX0101X. Bits 0, 5 and 6 of the first address byte are

disregarded by the device and can be either high or

low. The device will acknowledge after the first address

byte. A byte of don't care bits is then sent by the master,

with the device acknowledging afterwards. The third

byte sent to the device has bit7 (S/HE) set high and bit6

(R) set low. Bits 4 and 5 are don't cares and bits 0-3

define the number of blocks to be write protected. For

example, if three blocks are to be protected, the third

Note:

The High Endurance Block cannot be

changed after the security option has been

set. If the H.E. block is not programmed by

the user, the default location is the highest

block of memory.

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