24LC164-SLASHP datasheet(8/16 Pages) MICROCHIP

8 / 16 page

24LC164

DS21093I-page 8

 2004 Microchip Technology Inc.

FIGURE 7-1:

CURRENT ADDRESS READ

FIGURE 7-2:

RANDOM READ

FIGURE 7-3:

SEQUENTIAL READ

8.0

PIN DESCRIPTIONS

8.1

SDA Serial Address/Data Input/

Output

This is a bi-directional pin used to transfer addresses

and data into and data out of the device. It is an open

drain terminal. Therefore, the SDA bus requires a pul-

lup resistor to VCC (typical 10k

Ω for 100 kHz, 2kΩ for

400 kHz).

For normal data transfer SDA is allowed to change only

during SCL LOW. Changes during SCL HIGH are

reserved for indicating the START and STOP condi-

tions.

8.2

SCL Serial Clock

This input is used to synchronize the data transfer from

and to the device.

8.3

This pin must be connected to either VSS or VCC.

If tied to VSS, normal memory operation is enabled

(read/write the entire memory 000-7FF).

If tied to VCC, WRITE operations are inhibited. The

entire memory will be write-protected. Read operations

are not affected.

This feature allows the user to use the 24LC164 as a

serial ROM when WP is enabled (tied to VCC).

8.4

A0, A1, A2

These pins are used to configure the proper chip

address in multiple-chip applications (more than one

24LC164 on the same bus). The levels on these pins

are compared to the corresponding bits in the slave

address. The chip is selected if the compare is true.

Up to eight 24LC164s may be connected to the same

bus. These pins must be connected to either VSS or

VCC.

CONTROL

DATA (n)

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

S 1 A2 A1A0B2 B1B0

BYTE

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

WORD

ADDRESS (n)

CONTROL

BYTE

DATA (n)

1A2 A1A0B2B1B0

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

DATA (n)

DATA (n + 1)

DATA (n + 2)

DATA (n + X)

Note:

The level on A1 is compared to the

inverse of the slave address.

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