 2004 Microchip Technology Inc.

DS21170E-page 3

24C01SC/24C02SC

TABLE 1-2:

AC CHARACTERISTICS

FIGURE 1-2:

BUS TIMING DATA

Parameter

Symbol

Min.

Max.

Units

Remarks

Clock frequency

—

400

kHz

Clock high time

600

—

ns

Clock low time

1300

—

ns

SDA and SCL rise time

—

300

ns

(Note 1)

SDA and SCL fall time

—

300

ns

(Note 1)

Start condition hold time

600

—

ns

After this period the first clock

pulse is generated

Start condition setup time

600

—

ns

Only relevant for repeated

Start condition

Data input hold time

0—

ns

(Note 2)

Data input setup time

100

—

ns

Stop condition setup time

600

—

ns

Output valid from clock

—

900

ns

(Note 2)

Bus free time

1300

—

ns

Time the bus must be free

before a new transmission can

start

20 + 0.1

CB

250

ns

(Note 1), CB

= 100 pF

Input filter spike suppression

(SDA and SCL pins)

—50

ns

(Note 3)

Write cycle time

—

10

ms

Byte or Page mode

Endurance

—

1M

—

cycles

25°C, Vcc = 5V, Block mode

(Note 4)

Note 1:

Not 100% tested. CB = total capacitance of one bus line in pF.

2:

As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

3:

noise spike suppression. This eliminates the need for a TI specification for standard operation.

4:

This parameter is not tested but ensured by characterization. For endurance estimates in a specific

at www.microchip.com.

SCL

SDA

IN

SDA

OUT