24LC41A

DS21176D-page 8

 2003 Microchip Technology Inc.

FIGURE 3-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

FIGURE 3-2:

BUS TIMING START/STOP

FIGURE 3-3:

BUS TIMING DATA

FIGURE 3-4:

CONTROL BYTE ALLOCATION

DSCL

DSDA

(B)

(D)

(D)

(C)

START

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

or

MSCL

or

MSDA

MSCL

DSDA

START

STOP

or

MSCL

IN

or

MSDA

IN

DSCL

DSDA

DSDA

or

MSCL

IN

OR

MSDA

IN

OR

MSDA

OUT

B0, B1, and B2 are zeros for DDC Monitor Port. B1 and B2 are don’t care bits for the Microcontroller Access Port,

and B0 is used to select which of the two 256 word blocks of memory are to be accessed.

R/W

A

1

0

10B2

B1

B0

READ/WRITE

START

SLAVE ADDRESS