AM79C940 datasheet(79/144 Pages) AMD

79 / 144 page

Programmer’s Register Model (continued)

Addr Mnemonic

Contents

R/W

PHYCC

Physical Layer (PHY) Configuration Control

LNKFL

Link Fail–Reports 10BASE-T receive inactivity

DLNKTST

Disable Link Test–Force 10BASE–T port into Link Pass

REVPOL

Reversed Polarity–Reports 10BASE-T receiver wiring error

DAPC

Disable Auto Polarity Correction–Detection remains active

LRT

Low Receive Threshold–Extended distance capability

ASEL

Auto Select–Select 10BASE-T port when active, otherwise

AUI

RWAKE

Remote Wake–10BASE-T, AUI and EADI features active during

sleep

AWAKE

Auto Wake–10BASE-T receive and LNKST active during sleep

R/W

CHIPID

Chip Identification Register LSB–CHIPID [7:0]

CHIPID

Chip Identification Register MSB–CHIPID [15:8]

IAC

Internal Address Configuration

ADDRCHG Address Change–Write to PHYADDR or LOGADDR after ENRCV

–

PHYADDR Reset Physical Address pointer

LOGADDR Reset Logical Address pointer

–

R/W

–

Reserved

R/W as 0

LADRF

Logical Address Filter–8 bytes–8 reads or writes–LS Byte first

R/W as 0

PADR

Physical 6 bytes–6 reads or writes–LS Byte

first

R/W as 0

–

Reserved

R/W as 0

–

Reserved

R/W as 0

MPC

Missed Packet Counter–Number of receive packets missed

R/W as 0

–

Reserved

R/W as 0

RNTPC

Runt Packet Count–Number of runt packets addressed to this node

R/W as 0

RCVCC

Receive Collision Count–Number of receive collision frames on network

R/W as 0

–

Reserved

R/W as 0

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