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MCP23008-E/SS Arkusz danych(PDF) 21 Page - Microchip Technology |
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MCP23008-E/SS Arkusz danych(HTML) 21 Page - Microchip Technology |
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21 / 44 page ![]() © 2007 Microchip Technology Inc. DS21919D-page 21 MCP23008/MCP23S08 1.7 Interrupt Logic The interrupt output pin will activate if an internal interrupt occurs. The interrupt block is configured by the following registers: • GPINTEN – enables the individual inputs • DEFVAL – holds the values that are compared against the associated input port values • INTCON – controls if the input values are compared against DEFVAL or the previous values on the port • IOCON (ODR and INPOL) – configures the INT pin as push-pull, open-drain and active-level Only pins configured as inputs can cause interrupts. Pins configured as outputs have no affect on INT. Interrupt activity on the port will cause the port value to be captured and copied into INTCAP. The interrupt will remain active until the INTCAP or GPIO register is read. Writing to these registers will not affect the interrupt. The first interrupt event will cause the port contents to be copied into the INTCAP register. Subsequent interrupt conditions on the port will not cause an interrupt to occur as long as the interrupt is not cleared by a read of INTCAP or GPIO. 1.7.1 INTERRUPT CONDITIONS There are two possible configurations to cause interrupts (configured via INTCON): 1. Pins configured for interrupt-on-pin-change will cause an interrupt to occur if a pin changes to the opposite state. The default state is reset after an interrupt occurs. For example, an interrupt occurs by an input changing from 1 to 0. The new initial state for the pin is a logic 0. 2. Pins configured for interrupt-on-change from register value will cause an interrupt to occur if the corresponding input pin differs from the register bit. The interrupt condition will remain as long as the condition exists, regardless if the INTAP or GPIO is read. See Figure 1-6 and Figure 1-7 for more information on interrupt operations. FIGURE 1-6: INTERRUPT-ON-PIN- CHANGE FIGURE 1-7: INTERRUPT-ON-CHANGE FROM REGISTER DEFAULT GPx INT ACTIVE ACTIVE Port value is captured into INTCAP Read GPIU or INTCAP Port value is captured into INTCAP INT Port value is captured into INTCAP Read GPIU or INTCAP DEFVAL X X X X X 0 X X GP2 7 6 5 4 3 210 GP: ACTIVE ACTIVE (INT clears only if interrupt condition does not exist.) |
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