TDA8792 datasheet(8/20 Pages) PHILIPS

8 / 20 page

1996 Feb 21

Philips Semiconductors

Product speciﬁcation

3.3 V, 25 MHz 8-bit

analog-to-digital converter (ADC)

TDA8792

Notes

1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock

must not be less than 1 ns.

2. The analog bandwidth is defined as the maximum full-scale input sine wave frequency which can be applied to the

device. No glitches greater than 8 LSBs are observed in the reconstructed signal neither is there any significant

attenuation.

3. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale

input (square-wave signal) in order to sample the signal and obtain correct output data.

4. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8K acquisition points per equivalent

fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency

(NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB

× 6.02 + 1.76 dB.

5. Measurement carried out using video analyser VM700A, where the video analog signal is reconstructed through a

digital-to-analog converter.

6. Output data acquisition: the output data is available after the maximum delay time of td. In the event of 25 MHz clock

operation, the hardware design must be taken into account the td and th limits with respect to the input characteristics

of the acquisition circuit.

7. Maximum value standby mode start-up output delay time (HIGH-to-LOW transition):

EFFECTIVE BITS; see Figs 6 and 11; note 4

effective bits

fclk = 25 MHz

fi = 2.0 MHz

−

7.4

−

bits

fi = 4.43 MHz

−

7.3

−

bits

fi = 7.5 MHz

−

7.2

−

bits

fi = 10 MHz

−

7.0

−

bits

DIFFERENTIAL GAIN; see note 5

Gdiff

differential gain

fclk = 25 MHz;

PAL modulated ramp

−

1.5

−

DIFFERENTIAL PHASE; see note 5

diff

differential phase

fclk = 25 MHz;

PAL modulated ramp

−

0.5

−

deg

Timing (fclk = 25 MHz); see Fig.3 and note 6

tds

sampling delay time

−−

2ns

output hold time

−−

output delay time

3-state output delay times; see Fig.4

tdZH

enable HIGH

−

tdZL

enable LOW

−

tdHZ

disable HIGH

−

tdLZ

disable LOW

−

Standby mode output delay times

tdSTBLH

standby (LOW-to-HIGH transition)

−−

200

tdSTBHL

start-up (HIGH-to-LOW transition)

−−

note 7

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

100

7000

clk (MHz)

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