Data Sheet

ADL5205

Rev. A | Page 7 of 31

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

9

10

23

24

25

26

27

28

29

30

22

21

NOTES

1. DNC = DO NOT CONNECT. DO NOT CONNECT

TO THESE PINS.

2. THE EXPOSED PAD MUST BE CONNECTED TO

A LOW IMPEDANCE GROUND PLANE. THIS IS

THE GROUND (0V) REFERENCE FOR ALL THE

VOLTAGES IN TABLE 1.

PIN 1

INDICATOR

A4

A5

MODE1

MODE0

PM

DNC

SDIO/B5

SCLK/B4

CSA/A3

GS1/CSB/B3

DNC

VPOS

DNC

DNC

VPOS

DNC

VOUTB–

VOUTB+

VOUTA+

VOUTA–

ADL5205

TOP VIEW

(Not to Scale)

Figure 5. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

CSA/A3

Channel A Select in Serial Mode (CSA). When serial mode is enabled, a logic low selects Channel A.

Bit 3 for Channel A in Parallel Gain Control Interface Mode (A3).

2

A4

Bit 4 for Channel A in Parallel Gain Control Interface Mode (A4).

3

A5

Bit 5 for Channel A in Parallel Gain Control Interface Mode (A5).

4

MODE1

MSB for Mode Control. Use both the MODE0 and MODE1 pins to select parallel, SPI, or up/down

interface mode.

5

MODE0

LSB for Mode Control. Use both the MODE1 and MODE0 pins to select parallel, SPI, or up/down

interface mode.

6

PM

Power Mode. Set this pin to logic low to enable high performance mode, or logic high to enable

low power mode.

7, 19, 20, 23, 25, 26,

28, 31, 32

DNC

Do Not Connect. Do not connect to these pins.

8

SDIO/B5

Serial Data Input and Output in SPI Mode (SDIO).

Bit 5 for Channel B in Parallel Gain Control Interface Mode (B5).

9

SCLK/B4

Serial Clock Input in SPI Mode (SCLK).

Bit 4 for Channel B in Parallel Gain Control Interface (B4).

10

GS1/CSB/B3

MSB for the Gain Step Size Control in Up/Down Mode (GS1).

Channel B Select in Serial Mode (CSB). When serial mode is enabled, a logic low selects Channel B.

Bit 3 for Channel B in Parallel Gain Control Mode (B3).

11

GS0/FA_B/B2

LSB for the Gain Step Size Control in Up/Down Mode (GS0).

Fast Attack for Channel B (FA_B). In serial mode, a logic high on this pin attenuates Channel B

according to the FA bit values in the control register.

Bit 2 for Channel B in Parallel Gain Control Interface (B2).

12

UPDN_CLK_B/B1

Clock Interface for the Channel B Up/Down Function (UPDN_CLK_B).

Bit 1 for Channel B in Parallel Gain Control Interface Mode (B1).

13

UPDN_DAT_B/B0

Data Pin for the Channel B Up/Down Function (UPDN_DAT_B).

Bit 0 for Channel B in Parallel Gain Control Interface Mode (B0).