PACE1757ME datasheet(23/34 Pages) PYRAMID

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PACE 1757 M/ME

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Document # MICRO-10 REV B

SIGNAL DESCRIPTIONS (Continued)

BUS CONTROL

Mnemonic

Name

Description

TEST ON

System Test Enable

An active-LOW input, used to enable the execution of the System Test

built into the P1754, immediately after completetion of the PACE 1750 A/

AE initialization and before fetching any instructions from the user's

program.

TEST END

System Test End

An active-HIGH output indicating whether the PACE 1754 System Test

has been completed. Whenever the System Test is disabled by the

TEST

ON signal, the TEST END output will be at a logical "1" immediately after

reset is removed.

SC0-SC4

System Configuration

Inputs which are buffered onto IB0-IB4 when executing an I/O Read

Inputs

from I/O address 8410 (hex).

Data or instruction

An output signal that indicates whether the current bus cycle access is for

Data (HIGH) or Instruction (LOW). It is three-state during bus cycles not

assigned to the CPU. This line can be used as an additional memory

address bit for systems that require separate data and program memory.

Read or write

An output signal that indicates direction of data flow with respect to the

current bus master. A HIGH indicates a read or input operation and a

LOW indicates a write or output operation. The signal is three-state during

bus cycles not assigned to the CPU.

Memory or I/O

An output signal that indicates whether the current bus cycle is memory

(HIGH) or I/O (LOW). This signal is three-state during bus cycles not

assigned to the CPU.

RDYA_IN

Address ready In

An active HIGH input to the CPU that can be used to extend the address

phase of a bus cycle. When RDYA_IN is not active, wait states are

inserted by the P1750A/AE to accomodate slower memory or I/O devices.

This line is usually connected to RDYA_OUT unless the memory interface

logic requires the two RDYA signals remain discrete as an input and

output.

RDYA_OUT

Address Ready Out

An active HIGH output from the COMBO that indicates that there are no

wait states requested when STRBA is active. Wait states are inserted

when this signal becomes inactive during STRBA. Up to 3 wait states can

be inserted by programming an internal register. Three wait states are

inserted after reset (default).

RDYD

Data ready

An active HIGH signal to the CPU from the PIC that extends the data

phase of a bus cycle. When RDYD is not active, wait states are inserted

by the P1750A/AE to accomodate slower memory or I/O devices.

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