4

ICS9212-13

0272F—08/08/07

Absolute Maximum Ratings

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 4.0 V

Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Stresses above those listed under

Absolute Maximum Ratings may cause permanent damage to the device. These

ratings are stress specifications only and functional operation of the device at these or any other conditions above those

listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions

for extended periods may affect product reliability.

Parameters

Symbol

Min

Max

Unit

Supply Voltage

VDD

3.135

3.465

V

Refclk Input cycle time

10

40

ns

Input cycle-to-cycle Jitter

-

250

ps

Input Duty cycle over 10k cycles

40%

60%

Input frequency of modulation

30

33

kHz

Modulation index

0.25

0.5

%

Phase detector input cycle time at PDclk/M & Synclk/N

30

100

ns

Initial phase error at phase detector inputs

-0.5

0.5

Phase detector input duty cycle over 10k cycles

25%

75%

Input rise & fall times ( measured at 20%-80% of input voltage) for

PDCLK/M & SYNCLK/N,&REfCLK

-1

ns

Input capacitance at PDCLK/M,Synclk/N,&REFCLK

-7

pF

Input Capacitance matching at PCLK/M & SYNCLK/N

-0.5

pF

Input capacitance at CMOS pins

-10

pF

Input (CMOS) signal low voltage

-0.3

Vdd

Input (CMOS) signal high voltage

0.7

-

Vdd

REFCLK input low voltage

-

0.3

Vddi,R

REFCLK input high voltage

0.7

-

Vddi,R

Input signal low voltage for PD inputs and STOP

-

0.3

Vddi,PD

Input signal high voltage for PD inputs and STOP

0.7

-

Vddi,PD

Input supply referance for REFCLK

1.3

3.465

V

Input supply referance vfor PD inputs

1.3

3.465

V

Phase detector phase error for distributed loop measured at

PDCLK/M & SYNCLK/N(rising

-100

100

ps

Cycle cycle time

2.5

3.75

ns

Cycle-to-cycle jitter at Busclk/BUSCLKB (533 MHz)

-40

ps

Total jitter over 1 - 6 cycles (533MHz)

-30

ps

Phase aligner, phase step size (BSCLK/BUSCLKB)

1-

ps

PLL out put phase error when tracking SSC

-100

100

ps

Out put crossing-point voltage

1.3

1.8

V

Output voltage swing

0.4

0.6

V

Output high voltage

-2

V

Out put duty cycle over 10k cycle

DC

40%

60%

Output cycle -to-cycle duty cycle error

-50

ps

Output rise & fall times ( measured at 20%-80% of output voltage)

300

500

ps

Difference between rise and fall times on a single device(20%-80%)

-

100

ps

Opearting Supply Current

150

mA

Electrical Characteristics-input/supply/Outputs