P4C164L datasheet(6/11 Pages) PYRAMID

6 / 11 page

P4C164L

Page 6 of 11

Document # SRAM116 REV B

3ns

TIMING WAVEFORM OF WRITE CYCLE NO.2 (

CE CONTROLLED)(6)

* including scope and test fixture.

Note:

Because of the high speed of the P4C164L, care must be taken when

testing this device; an inadequate setup can cause a normal

functioning part to be rejected as faulty. Long high-inductance leads

that cause supply bounce must be avoided by bringing the V

CC and

ground planes directly up to the contactor fingers. A 0.01 µF high

frequency capacitor is also required between V

and ground.

To avoid signal reflections, proper termination must be used; for

example, a 50

Ω test environment should be terminated into a 50Ω load

with 1.77V (Thevenin Voltage) at the comparator input, and a 589

Ω

resistor must be used in series with D

OUT to match 639Ω (Thevenin

Resistance).

AC TEST CONDITIONS

Input Pulse Levels

Input Rise and Fall Times

Input Timing Reference Level

Output Timing Reference Level

Output Load

GND to 3.0V

1.5V

See Figures 1 and 2

Mode

I/O

Power

Standby

High Z

Standby

High Z

Standby

OUT

Disabled

High Z

Active

Read

OUT

Active

Write

High Z

Active

TRUTH TABLE

Figure 1. Output Load

Figure 2. Thevenin Equivalent

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