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PCA9502 Arkusz danych(PDF) 7 Page - NXP Semiconductors |
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PCA9502 Arkusz danych(HTML) 7 Page - NXP Semiconductors |
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7 / 25 page ![]() PCA9502_3 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 03 — 13 October 2006 7 of 25 NXP Semiconductors PCA9502 8-bit I/O expander with I2C-bus/SPI interface 9. I2C-bus operation The two lines of the I2C-bus are a serial data line (SDA) and a serial clock line (SCL). Both lines are connected to a positive supply via a pull-up resistor, and remain HIGH when the bus is not busy. Each device is recognized by a unique address whether it is a microcomputer, LCD driver, memory or keyboard interface and can operate as either a transmitter or receiver, depending on the function of the device. A device generating a message or data is a transmitter, and a device receiving the message or data is a receiver. Obviously, a passive function like an LCD driver could only be a receiver, while a microcontroller or a memory can both transmit and receive data. 9.1 Data transfers One data bit is transferred during each clock pulse (see Figure 4). The data on the SDA line must remain stable during the HIGH period of the clock pulse in order to be valid. Changes in the data line at this time will be interpreted as control signals. A HIGH-to-LOW transition of the data line (SDA) while the clock signal (SCL) is HIGH indicates a START condition, and a LOW-to-HIGH transition of the SDA while SCL is HIGH defines a STOP condition (see Figure 5). The bus is considered to be busy after the START condition and free again at a certain time interval after the STOP condition. The START and STOP conditions are always generated by the master. The number of data bytes transferred between the START and STOP condition from transmitter to receiver is not limited. Each byte, which must be eight bits long, is transferred serially with the most significant bit first, and is followed by an acknowledge bit. (see Figure 6). The clock pulse related to the acknowledge bit is generated by the master. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, while the transmitting device releases this pulse (see Figure 7). Fig 4. Bit transfer on the I2C-bus Fig 5. START and STOP conditions mba607 data line stable; data valid change of data allowed SDA SCL mba608 SDA SCL P STOP condition SDA SCL S START condition |
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