IDT71342LA55JI datasheet(10/14 Pages) IDT

10 / 14 page

6.42

IDT71342SA/LA

High-Speed 4K x 8 Dual-Port Static RAM with Semaphore

Industrial and Commercial Temperature Ranges

Timing Waveform of Semaphore Read After Write Timing, Either Side(1)

NOTE:

CE = VIH for the duration of the above timing (both write and read cycle).

NOTES:

1. D0R = D0L = VIL,

CER = CEL = VIH, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.

2. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

3. This parameter is measured from the point where R/

W "A" or SEM "A" goes HIGH until R/W "B" or SEM "B" goes HIGH.

4. If tSPS is violated, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.

Timing Waveform of Semaphore Condition(1,3,4)

A0 -A2

VALID ADDRESS

DATAIN VALID

DATAOUT

VALID

SEM

DATA0

tAW

tEW

tWR

tDW

tDH

tWP

tAS

tSWRD

tSOP

tAOE

tACE

tSAA

tOH

tSOP

Test Cycle

(Read Cycle)

Write Cycle

2721 drw 12

A0"A" -A2"A"

tSPS

W"A"

SEM"A"

SIDE

(2) "A"

A0"B" -A2"B"

W"B"

SEM"B"

SIDE

(2) "B"

MATCH

2721 drw 13

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