M69KB128AA datasheet(35/68 Pages) STMICROELECTRONICS

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M69KB128AA

7 Configuration registers

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7.4

Refresh Configuration Register

The role of the Refresh Configuration Register (RCR) is:

●

to define how the self refresh of the PSRAM array is performed,

●

to select the Deep Power-Down mode,

●

to enable Page Read operations.

Refer to Table 11 for the description of the Refresh Configuration Register Bits.

7.4.1

Page Mode Operation Bit (RCR7)

The Page Mode operation bit determines whether the Asynchronous Page Read mode is

enabled. At power-up, the RCR7 bit is set to ‘0’, and the Asynchronous Page Read mode is

disabled.

7.4.2

Deep Power-Down Bit (RCR4)

The Deep Power-Down bit enables or disables all refresh-related operations. The Deep Power-

Down mode is enabled when the RCR4 bit is set to ‘0’, and remains enabled until this bit is set

to ‘1’. At power-up, the Deep Power-Down mode is disabled.

See the Section 4.2: Deep Power-Down for more details.

7.4.3

Partial Array Refresh Bits (RCR2-RCR0)

The Partial Array Refresh bits allow refresh operations to be restricted to a portion of the total

PSRAM array. The refresh options can be full array, one half, one quarter, one eighth or none of

the array. These memory areas can be located either at the top or bottom of the memory array.

By default, the full memory array is refreshed.

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