CYII4SC1300AA-QSC datasheet(25/37 Pages) CYPRESS

25 / 37 page

IBIS4-1300

Document Number: 38-05707 Rev. *B

Page 25 of 37

Figure 20. Timing of X shift register and pixels read-out

On-chip generated electrical dark references.

The sensor outputs a electrical dark reference level after the

2nd falling edge on the clock (after sync).

At the end of the row readout, after EOS_X becomes low, the

sensor outputs the electrical dark reference voltage also, and

it remains present on the on the readout bus until the SIN goes

high.

Note that if the X-register is reset before the EOS is reached,

the dark reference is not put on the bus. Use the dark

reference of the beginning of the line instead.

Pixel readout

The same continuous 10 MHz clock drives CLK_ADC and

CLK_X. On the falling edge of CLK_X, a new pixel is selected

and propagates to the output amplifier. At the same time, the

ADC input is frozen by the falling edge on CLK_ADC. The

digital output has a delay of one pixel compared to the analog

signal. The digital output becomes valid between 25 to 50 ns

after the falling edge on CLK_ADC.

Figure 21. pixel timing

If the end of a row is reached, the sensor outputs an

end-of-scan (EOS) pulse during one pulse period. And the

electrical black reference level appears at the output for all

successive pulses. So, the same 10 MHz clock can drive

CLK_X and CLK_ADC.

DCREF on bus

Sync

Clock

Min 100 ns.

Min 25 ns

dark

nil

n-1

Dummy pixels

Output

Tp,adc

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