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ANALOG INPUTS

2.8V

Full-Scale

PP

2.8V

Full-Scale

PP

VINL+

or

VINR+

VINL

-

or

VINR

-

+1.95V

+1.95V

VOLTAGE REFERENCE

PCM4220

SBAS407A – DECEMBER 2006 – REVISED MAY 2007

PRODUCT OVERVIEW (continued)

The PCM4220 includes two analog inputs, referred to as the left and right channels. Each channel includes a

pair of differential voltage input pins. The left channel inputs are named VINL– (pin 10) and VINL+ (pin 11),

respectively. The right channel inputs are named VINR– (pin 2) and VINR+ (pin 3), respectively. Each pin of an

differential in the Electrical Characteristics table. Figure 35 shows the full-scale input range of the PCM4220,

with the input signals centered on the nominal common-mode voltage of +1.95V.

In a typical application, the front end is driven by a buffer amplifier or microphone/line level preamplifier.

Examples are given in the Input Buffer Circuits section of this datasheet. The analog inputs of the PCM4220

may be driven up to the absolute maximum input rating without instability. If the analog input voltage is expected

to exceed the absolute maximum input ratings in a given application, it is recommended that input clamping or

limiting be added to the analog input circuitry prior to the PCM4220 in order to provide protection against

damaging the device. Specifications for the analog inputs are given in the Electrical Characteristics and Absolute

Maximum Ratings tables of this data sheet.

Figure 35. Full-Scale Analog Input Range

The PCM4220 includes an on-chip, band-gap voltage reference. The band-gap output voltage is buffered and

then routed to the two delta-sigma modulators. The inclusion of an on-chip reference circuit enhances the

power-supply noise rejection of the PCM4220. The buffered reference voltage for each channel is filtered using

external capacitors. The capacitors are connected between VREFL (pin 15) and REFGNDL (pin 14) for the left

channel, and VREFR (pin 46) and REFGNDR (pin 47) for the right channel. Figure 36 illustrates the recommend

reference decoupling capacitor values and connection scheme.

The 10nF to 100nF capacitors in Figure 36 may be metal film or X7R/C0G ceramic chip capacitors. The 100

µF

capacitors may be polymer tantalum chip (Kemet T520 series or equivalent) or aluminum electrolytic.

The VREFL and VREFR pins are not designed for biasing external input circuitry. Two common-mode voltage

outputs are provided for this purpose, and are discussed in the following section.

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