PTV08040WAD datasheet(3/23 Pages) TI

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ELECTRICAL CHARACTERISTICS

PTV08040W

SLTS257A – SEPTEMBER 2005 – REVISED JANUARY 2007

A = 25°C, VI = 12 V, VO = 3.3 V, CI = 560 µF, CO = 150 µF, and IO = IOmax (unless otherwise stated)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

°C, Natural Convection

50(1)

Output current

8 V

≤ V

I ≤ 14 V

°C, 200 LFM airflow

48(1)

Input voltage range

Over IO range

VOtol

Set-point voltage tolerance

±2(2)

%VO

∆Reg

temp

Temperature variation

–40

°C < T

A < 85°C

±0.5

%VO

∆Reg

line

Line regulation

Over VI range

±3

∆Reg

load

Load regulation

Over IO range

±3

∆Reg

tot

Total output variation

Includes set-point, line, load, –40

°C ≤ T

A ≤ 85°C

±3(2)

%VO

∆Reg

adj

Output adjust range

0.8

3.6

RSET = 2.49 kΩ, VO = 3.3 V

RSET = 6.98 kΩ, VO = 2.5 V

RSET = 13.0 kΩ, VO = 2 V

RSET = 16.9 kΩ, VO = 1.8 V

Efficiency

IO = 35 A

RSET = 27.4 kΩ, VO = 1.5 V

RSET = 53.6 kΩ, VO = 1.2 V

RSET = 113.0 kΩ, VO = 1 V

RSET = open circuit, VO = 0.8 V

VO ripple (peak-to-peak)

20-MHz bandwidth

All voltages

mVPP

IOtrip

Overcurrent threshold

Reset, followed by auto-recovery

100

115

Transient response

1 A/µs load step, 50 to 100% IOmax, CO = 150 µF

trr

Recovery time

µs

∆V

VO over/undershoot

140

IILtrack

Track input current (pin 15)

Pin to GND

–0.13 (3)

dVtrack/dt

Track slew rate capability

CO ≤ CO(max)

V/ms

VI Increasing

7.5(4)

7.8

UVLO

Undervoltage lockout threshold

Pin 16 open

VI Decreasing

6.5(4)

Inhibit control (pin 16)

Referenced to GND

VIH

Input high voltage

2.5

Open(5)

VIL

Input low voltage

–0.2

0.5

IILinhibit

Input low current

Pin to GND

0.5

IIinh

Input standby current

Pin 16 to GND

f s

Switching frequency

Over VI and IO ranges

900

1050

1200

kHz

External input capacitance

560(6)

µF

Nonceramic

14,000(7)

Capacitance value

µF

External output capacitance

Ceramic

150(8)

750

Equivalent series resistance (nonceramic)

3(9)

Ω

2.7

MTBF

Reliability

Per Bellcore TR-332 50% stress, TA = 40°C, ground benigh

106 Hrs

(1)

See SOA curves or consult factory for appropriate derating.

(2)

The set-point voltage tolerance is affected by the tolerance of RSET. The stated limit is unconditionally met if RSET has a tolerance of 1%

with 100 ppm/

°C or better temperature stability.

(3)

This control pin has an internal pull-up to 5 V. A small, low-leakage (<100 nA) MOSFET or open-drain/collector voltage supervisor IC is

recommended to control this pin. For further information, see the related application section.

(4)

These are the default voltages. They may be adjusted using the UVLO Prog control input. See the Application Information section for

further guidance.

(5)

This control pin has an internal pull-up to 5 V. When left open-circuit the module operates when input power is applied. A small,

low-leakage (<100 nA) MOSFET is recommended to control this pin. For further information, see the related application section.

(6)

A minimum capacitance of 560-µF is required at the input for proper operation. For best results, 1000 µF is recommended. The

capacitance must be rated for a minimum of 300 mArms of ripple current.

(7)

This is the calculated maximum. The minimum ESR requirement often results in a lower value. For further information, see the related

application section.

(8)

A minimum value of output capacitance is required for proper operation. Adding additional capacitance at the load further improves

transient response.

(9)

This is the typical ESR for all the electrolytic (nonceramic) output capacitance. Use 5 m

Ω as the minimum when using manufacturer's

max-ESR values to calculate.

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