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SC16C852LIB Arkusz danych(PDF) 48 Page - NXP Semiconductors |
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SC16C852LIB Arkusz danych(HTML) 48 Page - NXP Semiconductors |
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48 / 60 page ![]() SC16C852L_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 25 January 2007 48 of 60 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder Fig 20. Receive ready timing in FIFO mode (16 mode) D0 D1 D2 D3 D4 D5 D6 D7 002aac614 first byte that reaches the trigger level stop bit parity bit td(stop-RXRDY) RXA, RXB RXRDYA, RXRDYB IOR active data ready start bit data bits (0 to 7) active td(IOR-RXRDYH) Fig 21. Receive ready timing in FIFO mode (68 mode) D0 D1 D2 D3 D4 D5 D6 D7 002aac621 first byte that reaches the trigger level stop bit parity bit td(stop-RXRDY) RXA, RXB RXRDYA, RXRDYB CS (read) active data ready start bit data bits (0 to 7) active td(CS-RXRDYH)R |
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