Block Diagram

Note: The address/data pins are available in various combinations (see the address/data table).

Pin Assignment

Pin Description

Pin Name

I/O

Internal

Connection

Description

A0~A11 (HT12F)

I

NMOS

Transmission Gate

Input pins for address A0~A11 setting

These pins can be externally set to VSS or left open.

A0~A7 (HT12D)

Input pins for address A0~A7 setting

These pins can be externally set to VSS or left open.

D8~D11 (HT12D)

O

CMOS OUT

Output data pins, power-on state is low.

DIN

I

CMOS IN

Serial data input pin

VT

O

CMOS OUT

Valid transmission, active high

OSC1

I

Oscillator

Oscillator input pin

OSC2

O

Oscillator

Oscillator output pin

VSS

¾¾

Negative power supply, ground

VDD

¾¾

Positive power supply

HT12D/HT12F

Rev. 1.10

2

November 18, 2002

D a t a S h i f t

R e g i s t e r

O s c i l l a t o r

B u f f e r

S y n c . D e t e c t o r

D i v i d e r

C o m p a r a t o r

C o m p a r a t o r

B u f f e r

T r a n s m i s s i o n G a t e C i r c u i t

D a t a D e t e c t o r

C o n t r o l L o g i c

O S C 1

O S C 2

D I N

V D D

V S S

V T

D a t a

L a t c h C i r c u i t

A d d r e s s

8 - A d d r e s s

4 - D a t a

1 2 - A d d r e s s

0 - D a t a

A 0

A 1

A 2

A 3

A 4

A 5

A 6

A 7

V S S

V D D

V T

O S C 1

O S C 2

D I N

D 1 1

D 1 0

D 9

D 8

1

2

3

4

5

6

7

8

9

1 8

1 7

1 6

1 5

1 4

1 3

1 2

1 1

1 0

1 2 - A d d r e s s

0 - D a t a

A 0

A 1

A 2

A 3

A 4

A 5

A 6

A 7

V S S

V D D

V T

O S C 1

O S C 2

D I N

A 1 1

A 1 0

A 9

A 8

1

2

3

4

5

6

7

8

9

1 8

1 7

1 6

1 5

1 4

1 3

1 2

1 1

1 0

1

2

3

4

5

6

7

8

9

1 0

2 0

1 9

1 8

1 7

1 6

1 5

1 4

1 3

1 2

1 1

N C

V D D

V T

O S C 1

O S C 2

D I N

A 1 1

A 1 0

A 9

A 8

N C

A 0

A 1

A 2

A 3

A 4

A 5

A 6

A 7

V S S

8 - A d d r e s s

4 - D a t a

1

2

3

4

5

6

7

8

9

1 0

2 0

1 9

1 8

1 7

1 6

1 5

1 4

1 3

1 2

1 1

N C

V D D

V T

O S C 1

O S C 2

D I N

D 1 1

D 1 0

D 9

D 8

N C

A 0

A 1

A 2

A 3

A 4

A 5

A 6

A 7

V S S

H T 1 2 .

2 0 S O P - A

H T 1 2 .

1 8 D I P - A

H T 1 2 D

1 8 D I P - A

H T 1 2 D

2 0 S O P - A