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HT24LC02 Arkusz danych(PDF) 3 Page - Holtek Semiconductor Inc |
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HT24LC02 Arkusz danych(HTML) 3 Page - Holtek Semiconductor Inc |
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3 / 12 page ![]() A.C. Characteristics Symbol Parameter Remark Standard Mode* VCC=5V ±10% Unit Min. Max. Min. Max. fSK Clock Frequency ¾¾ 100 ¾ 400 kHz tHIGH Clock High Time ¾ 4000 ¾ 600 ¾ ns tLOW Clock Low Time ¾ 4700 ¾ 1200 ¾ ns tr SDA and SCL Rise Time Note ¾ 1000 ¾ 300 ns tf SDA and SCL Fall Time Note ¾ 300 ¾ 300 ns tHD:STA START Condition Hold Time After this period the first clock pulse is generated 4000 ¾ 600 ¾ ns tSU:STA START Condition Setup Time Only relevant for repeated START condition 4000 ¾ 600 ¾ ns tHD:DAT Data Input Hold Time ¾ 0 ¾ 0 ¾ ns tSU:DAT Data Input Setup Time ¾ 200 ¾ 100 ¾ ns tSU:STO STOP Condition Setup Time ¾ 4000 ¾ 600 ¾ ns tAA Output Valid from Clock ¾¾ 3500 ¾ 900 ns tBUF Bus Free Time Time in which the bus must be free before a new transmission can start 4700 ¾ 1200 ¾ ns tSP Input Filter Time Constant (SDA and SCL Pins) Noise suppression time ¾ 100 ¾ 50 ns tWR Write Cycle Time ¾¾ 5 ¾ 5ms Note: These parameters are periodically sampled but not 100% tested * The standard mode means VCC= 2.2V to 5.5V at Ta= 0 °Cto+70°C, VCC= 2.4V to 5.5V at Ta= -40°Cto+85°C For relative timing, refer to timing diagrams HT24LC02 Rev. 1.30 3 June 27, 2007 |
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